Synchronized devices sample or receive data by sampling the data at sampling points that are usually defined by a clock signal. In order to sample the data correctly timing constraints (such as setup period and hold period) are imposed. These timing constraints define the timing difference between data signal transitions and clock signal transitions. In a nutshell, sampling requires that there is a minimal timing difference between said transitions.
Synchronizers are commonly used for interfacing different circuits that reside into clock domains that are mutually asynchronous. Typically, a synchronizer receives a data signal from an asynchronous circuit that is not clocked at all, but this is not necessarily so. This a-synchronicity complicates the imposition of the mentioned above timing constraints. Accordingly, the synchronizer can sample the data signal while the data signal is not properly defined—it is within a meta-stable range. The synchronizer will eventually converge into a stable position but the convergence period is not indeterminable.
Various methods and devices were suggested for coping with metastability. Some include level sensitive circuits, some include complex circuits that are characterized by a finite and predictable metastable time and some include oscillation suppressors and decentration circuits. The following U.S. patents, all being incorporated herein by reference, illustrates some prior art circuits: U.S. Pat. No. 482,093 of Sowell et al., U.S. Pat. No. 6,072,346 of Ghahremani and U.S. Pat. No. 5,045,801 of Mowery.
There is a need to provide efficient methods and devices for methods handling meta-stable signals.